Method for manufacturing a semiconductor device having lateral MOSFET (LDMOS)

ABSTRACT

In an LDMOS, an n-type region  6,  which is formed to have a concentration higher than that of an n-type substrate  1  and whose concentration gradually increases from the n-type substrate  1  to an n +  type drain region  5,  is disposed so as to surround the n + -type drain region  5.  Further, a p + -type contact region  9  disposed adjacent to an n + -type source region  8  is formed so as to extend below the n + -type source region  8  so that a parasitic transistor formed by the n + -type source region  8,  a p-type base region  7  and the n-type substrate  1  is hardly turned ON.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] This application is based on Japanese Patent Application Nos.2000-106991 filed on Apr. 7, 2000, and 2000-398749, filed on Dec. 27,2000, the contents of which are incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The present invention relates to a lateral MOSFET (LDMOS) inwhich a source region and a drain region are arrayed in the lateraldirection of a semiconductor substrate.

[0004] 2. Related Arts

[0005] A power element has a structure in which several tens thousand toseveral hundreds thousand small LDMOSs are connected in parallel ingeneral and these LDMOSs are operated at the same time to obtain anoutput.

[0006] However, there has been a problem that when a large current suchas ESD (electrostatic discharge) flows through the LDMOSs instantly, theelement is destroyed or wires connected to the element melt because thelarge current does not flow though all of the LDMOSs uniformly, but thelarge current concentrates on some of the LDMOSs.

[0007] Therefore, it has been required to improve a capacity for ESDsurge. A high capacity for ESD surge of around 10 kV/mm² has beenrequired in particular in the field of vehicular application. Although amethod of adding external devices such as a capacitor to the outside ofthe IC chip has been adopted in the past to improve the capacity for ESDsurge, such method inevitably increases the cost.

SUMMARY OF THE INVENTION

[0008] In view of the problem described above, it is an object of theinvention to provide a semiconductor device whose capacity for ESD surgecan be improved.

[0009] In order to achieve the above-mentioned object, the inventorshave studied following points.

[0010] A non-uniformity of current at the time of ESD surge occurs dueto variations of electrode resistance on a chip for example. Thenon-uniformity of current occurs because of a wire bonding section, thatis, a current flow change based on a wire resistance. In concrete, acurrent carrying through a LDMOS near the wire bonding section flowswell because the wire resistance is small. While a current carryingthrough a LDMOS far from the wire bonding section does not flow wellbecause the wire resistance is large in comparison with the LDMOS nearthe wire bonding section.

[0011] A circuit in which an ESD surge generating circuit 50 a shown inFIG. 13 is connected to an LDMOS chip 50 b in which three cells ofLDMOSs 51 a, 51 b and 51 c are provided, i.e., a circuit in which thethree cells of the LDMOSs 51 a through 51 c are connected to a highvoltage generating circuit and resistors 52 and 53 which correspond tothe resistance of wires according to a distance from a wire bondingsection are disposed among the drain terminals of the respective LDMOSs51 a through 51 c.

[0012] When a switch 54 is turned ON, power is supplied from a highvoltage power source 55 and a capacitor 56 is charged in the surgegenerating circuit 50 a. Then, when a switch 57 is turned ON afterturning OFF the switch 54, an ESD surge current flows through the threecells of the LDMOSs 51 a through 51 c, respectively. Since an L load 58is included within the circuit, a large current caused by the ESD surgecurrent flows through the three cells of the LDMOSs 51 a through 51 c atthis time.

[0013] Then, when the inventors conducted a simulation analysis withsuch circuit, drain currents Id1, ID2 and Id3 of the respective MOSFET51 a through 51 c and drain voltages Vd1, Vd2 and Vd3 of the respectiveMOSFET 51 a through 51 c were represented as shown in FIG. 14.

[0014] As it is apparent from this chart, although the drain current Id1flowing through the LDMOS 51 a directly connected with the power supplyline suddenly increases from the start of a concentration of current,the drain currents Id2 and Id3 flowing through the LDMOSs 51 b and 51 cconnected to the power supply line via the resistors 52 and 53 decrease.

[0015] It is because a current-voltage characteristics of the LDMOS hasa negative resistance. Namely, the current flowing through the LDMOS 51a comes into values on a negative resistance region so that a positivefeedback occurs and a drain voltage drops when the concentration ofcurrent starts as indicated by the upward arrow in the in FIG. 15, whilecurrents flowing through each of the LDMOSs 51 b and 51 c does not comeinto the values on the negative resistance region, thereby dropping thecurrents flowing through the LDMOSs 51 b and 51 c with drop of eachdrain voltage as indicated by a downward arrow in FIG. 15.

[0016] The negative resistance occurs when a voltage between a sourceand a drain decreases although the drain current is still increasing.This voltage drop occurs due to the fact that a width of the depletionlayer at a PN junction does not vary although the drain current is stillincreasing.

[0017] That is, although the voltage between the source and the draincorresponds to an integral value of electric field strength between thesource and the drain, the voltage between the source and the drain isdecreased because the field strength drops when the drain currentbecomes a large current. As a result, the negative resistance occurs.

[0018] The inventors obtained results shown in FIGS. 16A and 16B bysimulating changes of a distribution of field strength under twodifferent conditions, i.e., the drain current is 20A and the draincurrent is 200A. The field strength at a part A-A′ in FIGS. 16A and 16Bis shown in FIG. 17. It also can be seen from the result that thevoltage between the source and the drain, which corresponds to theintegral value (area) of the field strength between the source and thedrain, decreases when the drain current increases, thus causing thenegative resistance.

[0019] As described above, the LDMOS has the negative resistance shownin FIG. 15. As a resistance of the LDMOS 51 a is inside of the negativeresistance region, a current flowing through the LDMOS 51 a increaseswith a decrease of voltage applied between a source and a drain of theLDMOS 51 a. However, resistance between a source region and a drainregion in each of the LDMOSs 51 b and 51 c is outside of the negativeresistance region, so that the current applied to each of the LDMOSs 51b and 51 c decreases.

[0020] Therefore, the ESD surge current concentrates on the LDMOS 51 a,thus destroying the element of the LDMOS 51 a or melting a wireconnected with the LDMOS 51 a.

[0021] After all, it is possible to prevent the local concentration ofthe ESD surge current and to improve the capacity for ESD surge byimproving the negative resistance described above. The inventors studiedabout the improvement of the negative resistance.

[0022] The negative resistance occurs while the drain current is stillincreasing although a width of the depletion layer at a PN junction doesnot vary as described above. Accordingly, the inventors considered thatthe negative resistance may be improved by modifying a structure bywhich the width of the depletion layer formed at the PN junction may isacquired, i.e., by modifying a structure in which the depletion layerhardly extends in the vicinity of the drain region.

[0023] Then, as a result of trials and errors, the inventors devised anLDMOS shown in FIG. 18 as the structure satisfying the above conditions.

[0024] The LDMOS has a structure in which a drain region is surroundedby an n-type region 6. An impurity concentration in the n-type region 6is set so that the impurity concentration gradually increases from asemiconductor layer 1 to the drain region 5. In other words, the closerto the drain region 5 centering on the drain region 5, the denser theconcentration of n-type impurity concentration in the n-type region 6becomes.

[0025] The inventors conducted a simulation analysis to simulate how thenegative resistance changes by changing the impurity concentration inthe n-type region 6, or more concretely an impurity concentration in asurface part of the n-type region 6 (hereinafter referred to as asurface concentration).

[0026]FIG. 19 shows a result. It is noted that the above-mentionedanalysis was carried out by the simulation under a diffusion conditionthat the surface concentration in the n-type region 6 is changed withina hatched range in FIG. 20. More specifically, the analysis was carriedout by changing the surface concentration in the n-type region 6 withina range from a surface concentration which is equal to the case when non-type region 6 is provided to a surface concentration of approximately2×10¹⁷ cm⁻³ under a diffusion condition that a concentration at thedepth of 2 μm from the surface of the substrate turns out to be{fraction (1/10)} of the surface concentration as shown in FIG. 20.

[0027] It can be seen from this result that two inflection points 1 and2 exist in the current-voltage characteristics. It is considered thatone of factors for these two inflection points 1 and 2 may be that aparasitic transistor formed by the source region 8, the base region 7and a drift region (n-type substrate 1) turns ON or that a high electricfield region reaches to the drain region 5.

[0028] Then, in order to analyze the factor of the two inflection points1 and 2, the source region 8 of the LDMOS shown in FIG. 18 waseliminated to have a diode structure and a negative resistance of thisdiode structure was checked out. The result is shown in FIG. 22.

[0029] As it is apparent from this result, there is only the inflectionpoint 2 in the diode structure. It can be seen from this result that theinflection point 1 among the two inflection points 1 and 2 was caused bythe parasitic transistor.

[0030] Then, it can be seen that the inflection point 2 shifts to highvalues of the current Id with increase of the surface concentration inthe n-type region 6. It also can be seen from FIG. 22 that theinflection point 2 occurs by a breakdown of the PN junction at a timewhen an expansion of the depletion layer is suppressed due to a highconcentration of the drain region after reaching the drain region,whereby an electric field becomes strong.

[0031] On this account, it is possible to arrange such that a currentvalue, from which a resistance between the source region and the drainregion of the LDMOS change into the negative resistance region,increases. In other words, the resistance between the source region andthe drain of the LDMOS hardly come into the negative resistance regionin the current-voltage characteristics by increasing the surfaceconcentration.

[0032] Accordingly, it is possible to prevent the resistance between thedrain region and the source region of one or some of the LDMOSs frombeing in the negative resistance region in a low level of the currentflowing through the LDMOS and to prevent the large current from locallyflowing, thereby improving the capacity for the ESD surge.

[0033] Meanwhile, it is considered that the remaining inflection point 2may occur due to the fact that a high electric field region extends andreaches to the drain region 5. Then, the inventors simulated adistribution of electric field strength to check out how the highelectric field region extends by setting the surface concentration inthe n-type region 6 at a predetermined value (here, 5×10¹⁶ cm⁻³) and bychanging the value of drain current. As a result, the result shown inFIG. 23b was obtained. It is noted that a horizontal axis of thedistribution of field strength in FIG. 23b corresponds to a lateraldirection of the diode structure shown in FIG. 23c.

[0034] As it is apparent from this chart, the high electric field regionextends toward the drain region with an increase of the drain current.Therefore, it is possible to prevent the resistance between the drainregion and the source region of one or some of the LDMOSs from being innegative resistance region even when the ESD surge occurs by arrangingso that the high electric field region reaches to the drain region whenthe drain current becomes equal to or greater than that at the time ofESD surge (200 A for example).

[0035] As described above, it is possible to increase the current valuewhen the resistance between the drain region and the source region ofthe LDMOS is in the negative resistance region by increasing the surfaceconcentration of the n-type region.

[0036] Further, it is possible to prevent the resistance between thedrain region and the source region of the LDMOS from being in thenegative resistance region more by setting the surface concentration ofthe n-type region so that the high electric field region reaches to thedrain region when the drain current becomes equal to or greater thanthat at the time of ESD surge.

[0037] It is also possible to sift the inflection point 1 which also maybe caused by the parasitic transistor and to prevent the resistancebetween the drain region and the source region of the LDMOS from beingin the negative resistance region by constructing the LDMOS having thestructure in which the parasitic transistor hardly turns ON.

[0038] According to the present invention, a first conductive typeregion is provided between a drain region and a base region on a surfacelayer part of a semiconductor layer. The first conductive type region isconstructed so that its concentration is higher than that of thesemiconductor layer and this concentration gradually increases from thesemiconductor layer to the drain region.

[0039] As mentioned above, a current value at which a resistance betweenthe source region and the drain region of a LDMOS comes into thenegative resistance region can be increased and the capacity for ESDsurge can be improved by disposing the first conductive type regionbetween the drain region and the base region.

[0040] According to another aspect of the present invention, a secondconductive type region is provided so as to contact to a lower part ofthe source region, the second conductive type region has a concentrationhigher than that of the base region.

[0041] The parasitic transistor hardly turns ON by providing the secondconductive type region. Thereby, it is possible to prevent theresistance between the drain region and the source region of the LDMOSfrom coming into the negative resistance region and to improve thecapacity for ESD surge.

[0042] In this case, it is preferable to dispose the second conductivetype region away from the channel region.

[0043] It is preferable to form the first conductive type region beforeforming the drain region on a surface layer part of a semiconductorlayer

[0044] It is preferable to form the first conductive type region byion-implanting first conductive type impurity at a dosage of 1×10¹⁴ cm⁻²or less. With such dosage, it is possible to make a concentration of thefirst conductive type region to a degree such that a sustaincharacteristics becomes positive reliably.

[0045] It is preferable to set the dosage of the first conductive typeimpurity at 2×10¹³ cm⁻² or more. With such dosage, it is possible tomake the concentration of the first conductive type region to a degreesuch that a depletion layer extending within the first conductive typeregion does not reach to the drain region.

[0046] It is preferable to set a depth of the first conductive typeregion at 2 to 4 μm. It is possible to prevent an interface of an oxidefilm (LOCOS (LOCal Oxidation of Silicon) film) from becoming unstabledue to a suction (absorption) of the impurity to the oxide film bysetting the depth of the first conductive type region at 2 μm or more asdescribed above. It is also possible to prevent ON resistance fromincreasing due to an increase of a gap between the source and the drainby setting the first conductive type region at 4 μm or less.

[0047] It is preferable to carry out the step for forming the contactregion by high acceleration ion implantation. In this way, a contactregion is formed at a position deeper than the surface portion thesemiconductor layer. Therefore, a concentration in a channel part may besuppressed low even if a concentration of the contact region isincreased.

BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Other objects, features and advantages of the present inventionwill become more apparent from the following detailed description madewith reference to the Note accompanying drawings. In the drawings:

[0049]FIG. 1 shows a sectional view of an LDMOS in a first embodiment.

[0050]FIG. 2 is a graph showing the concentration profile in part A-A′in FIG. 1.

[0051]FIG. 3 is a chart showing the current-voltage characteristics whenthe LDMOS shown in FIG. 1 breaks down.

[0052]FIG. 4 is a simulating chart for drain current and drain voltageof the LDMOS shown in FIG. 1.

[0053]FIGS. 5A through 5C are schematic sectional view of the LDMOSshown in FIG. 1 illustrating manufacturing steps of a first embodiment.

[0054]FIGS. 6A through 6C are schematic sectional view of the LDMOSshown in FIG. 1 illustrating manufacturing steps of a first embodiment.

[0055]FIGS. 7A through 7C are schematic sectional view of the LDMOSshown in FIG. 1 illustrating manufacturing steps of a first embodiment.

[0056]FIGS. 8A through 8C are schematic sectional view of the LDMOSshown in FIG. 1 illustrating manufacturing steps of a first embodiment.

[0057]FIG. 9 is a schematic sectional view of a LDMOS in anotherembodiment.

[0058]FIG. 10 is a sectional structure of a LDMOS in another embodiment.

[0059]FIG. 11 is a sectional structure of a LDMOS in another embodiment.

[0060]FIG. 12 is a sectional view of a MOS transistor which is formedtogether with the LDMOS of the another embodiment.

[0061]FIG. 13 is a circuit diagram for generating an ESD surge.

[0062]FIG. 14 is a simulating chart for a drain current and a drainvoltage by using the circuit shown in FIG. 13.

[0063]FIG. 15 is a graph explaining the negative resistance of theLDMOS.

[0064]FIGS. 16A and 16B are graphs showing distributions of electricfield intensity when current values are different.

[0065]FIG. 17 is a graph showing field intensity in part A-A′ in FIGS.16A and 16B.

[0066]FIG. 18 is a sectional view of an LDMOS.

[0067]FIG. 19 is a chart showing a relationship between a change ofconcentration and the negative resistance of the LDMOS.

[0068]FIG. 20 is a concentration profile of the LDMOS shown in FIG. 18.

[0069]FIG. 21 is a schematic sectional view of a device having a diodestructure in which a source region is eliminated from the LDMOS shown inFIG. 18.

[0070]FIG. 22 is a chart showing the negative resistance of the diodestructure shown in FIG. 21.

[0071]FIG. 23A is a graph explaining the negative resistance of thedevice shown in FIG. 21;

[0072]FIG. 23B is a graph showing field intensity in the device shown inFIG. 21; and

[0073]FIG. 23C is a schematic sectional view explaining a range of Yaxis in FIG. 23B.

DESCRIPTION OF THE PREFERRED EMBODIMENT

[0074] (First Embodiment)

[0075]FIG. 1 shows the sectional structure of an LDMOS to which oneembodiment of the present invention is applied. The structure of theLDMOS of this embodiment will be explained below based on FIG. 1.

[0076] The LDMOS is formed on an SOI substrate in which a n-typesubstrate (semiconductor layer) 1 is pasted with a p-type substrate 2with an insulating film 3 made of a silicon oxide film interposedtherebetween.

[0077] An impurity concentration of the n-type substrate 1 isapproximately between 1×10¹⁵ and 1×10¹⁶cm⁻³. An insulating film 4 isformed on a surface of the n-type substrate 1. An n⁺-type drain region 5whose concentration is high is formed on the surface layer of the n-typesubstrate 1 so as to contact with the insulating film 4. Then, an n-typeregion 6 is formed so as to surround the n⁺-type drain region 5. Then-type region 6 is formed so as to extend below the insulating film 4.An impurity concentration of the n-type region 6 is set so that theconcentration gradually increases from the substrate 1 to the n⁺-typedrain region 5.

[0078] A p-type base region 7 is also formed on the surface layer of then-type substrate 1. The p-type base region 7 reaches a vicinity of anedge of the insulating film 4. It is noted that a depth of the p-typebase region 7 is partly deep. This deepened region acts as a deep baselayer.

[0079] An n⁺-type source region 8 is formed on a surface layer part ofthe p-type base region 7 so as to separate from the insulating film 4. Ap⁺-type contact region 9 is also formed on the surface layer part of thep-type base region 7 so as to contact with the n⁺-type source region 8.The p⁺-type contact region 9 is disposed on an opposite side from then⁺-type drain region 5 interposing the n⁺-type source region 8therebetween, and extends below an under layer part of the n⁺-typesource region 8.

[0080] A gate insulating film 10 is disposed on the surface of thep-type base region 7 interposed between the n⁺-type source region 8 andthe n⁺-type drain region 5. A gate electrode 11 is provided on the gateinsulating film 10.

[0081] A MOS operation is conducted by setting a surface portion of thep⁺-type base region 7 positioned below the gate electrode 11 as achannel region and by setting the n-type substrate 1 as a n-type driftregion.

[0082] An interlayer insulating film 12 is disposed so as to cover thegate electrode 11. A source electrode 13 a drain electrode 14 arepatterned on the interlayer insulating film 12. The source electrode 13is connected with the n⁺-type source region 8 and the p⁺-type contactregion 9. The drain electrode 14 is connected with the n⁺-type drainregion 5 through a contact hole formed in the interlayer insulating film12.

[0083] It is noted that although not shown, a surface of the SOIsubstrate is covered by a protecting film or the like so as to cover thesource electrode 13 and the drain electrode 14.

[0084] A relationship on concentration of respective components of theLDMOS will be explained by showing the concentration profile at a partA-A′ in FIG. 1.

[0085] As shown in FIG. 2, a concentration of n-type impurity is veryhigh in the n⁺-type source region 8 and the n⁺-type drain region 5. Onthe contrary, although concentration in the n-type region 6 is not ashigh as the n⁺-type source region 8 and the n⁺-type drain region 5, theconcentration is higher than that of the n-type substrate 1. Thisconcentration is arranged so that the concentration gradually increasesfrom the n-type substrate 1 to the n⁺-type drain region 5. In concrete,the n-type region 6 has a concentration gradient so that a surfaceconcentration at a part of the n-type region 6 contacting with then⁺-type drain region 5 is approximately 5×10¹⁶ to 2×10¹⁷ cm⁻³ forexample.

[0086] That is, the LDMOS of the this embodiment is constructed so thatthe n-type region 6 whose concentration is higher than that of then-type substrate 1 is formed so as to surround the n⁺-type drain region5 and so that a high electric field region extending though the n-typeregion 6 reaches to the n⁺-type drain region 5 when drain currentbecomes equal to or greater than that at the time of ESD surge.

[0087] Thus, the high electric field region is suppressed to extend evenif large drain current is likely to flow by forming the n-type region 6whose concentration is higher than that of the n-type substrate 1 so asto surround the n⁺-type drain region 5. That is, the high electric fieldregion hardly reaches the n⁺-type drain region 5. As a result, itbecomes possible to keep a voltage applied between the source region 8and the drain region 5 corresponding to an integral value of electricfield strength between the source region 8 and the drain region 5 high.

[0088] Therefore, it becomes possible to prevent a decrease of thevoltage between the source region 8 and the drain region 5 caused by acondition that a extension of a high electric field region caused whenthe ESD surge occurs reaches to the n⁺-type drain region 5. On thisaccount, a current value when the resistance between the source region 8and the drain region 5 of the LDMOS is inside of a negative resistanceregion can be large. Thus, it becomes possible to improve one of twoinflection points shown in FIG. 19 and to prevent the resistance betweenthe source region 8 and the drain region 5 of the LDMOS from beinginside of the negative resistance region even at the time of ESD surge.

[0089] Further, it is possible to increase the current value when theresistance between the source region 8 and the drain region 5 of theLDMOS comes into the negative resistance region without increasing theconcentration of the n-type region 6 too much by controlling theimpurity concentration of the n-type region 6 so that the high electricfield region reaches to the n⁺-type drain region 5 when the draincurrent increases to be equal to or greater than a value in occurringthe ESD surge.

[0090] Meanwhile, the LDMOS of this embodiment is constructed so thatthe p⁺-type contact region 9 extends below the n⁺-type source region 8.More specifically, the p⁺-type contact region 9 is formed so as toextend below the n⁺-type source region 8 and so as not to reach thechannel region. That is, the p⁺-type contact region 9 is formed so as toextend below the n⁺-type source region 8 to such a degree that thep⁺-type contact region 9 does not affect in forming the channel region.

[0091] The high concentrate p⁺-type region is disposed between then⁺-type source region 8 and the p-type base region 7 and a PNP parasitictransistor formed by the n⁺-type source region 8, the p-type base region7 and the n-type substrate 1 (n-type drift region) hardly turns ON byconstructing as described above.

[0092] Thereby, it becomes possible to improve the inflection pointcaused by the parasitic transistor and to prevent the LDMOS from beingin a state of the negative resistance region further by constructing theLDMOS such that the parasitic transistor will not turn ON.

[0093] A current-voltage (Vd-Id) characteristics of the LDMOSconstructed as described above at the time of breakdown is shown in FIG.3. A characteristics that a voltage Vd is not reduced even if a draincurrent Id is still increasing is obtained in a scope when a maximumvalue of the drain current Id which may occur at the time of ESD surgeis assumed to be 200 A or less. That is, the inventor obtained thecharacteristics that the current value coming into the negativeresistance region is 200 A or more.

[0094] Then, when the inventor simulated and analyzed a LDMOSconstructed as described above by connecting three cells of LDMOSs asshown in FIG. 13. Drain currents Id1, Id2 and Id3 of the respectiveLDMOSs 51 a through 51 c and the drain voltages Vd1, Vd2 and Vd3 of therespective LDMOSs 51 a through 51 c were represented as shown in FIG. 4.

[0095] As it is apparent from this graph, the drain current Id1 flowingthrough the LDMOS 54 a directly connected with a power supply line isalmost the same values as the drain currents Id2 and Id3 flowing throughthe LDMOSs 54 b and 54 c connected with the power supply line throughresistors 55 and 56. Namely, it not occurred that only the drain currentId1 suddenly increases. Each of the drain voltages Vd1, Vd2 and vd3 doesnot also drop even though the drain currents Id1 through Id3 increase.

[0096] Thus, the capacity for the ESD surge of the LDMOS may be improvedby constructing as described above.

[0097] It is noted that although the LDMOS of the present embodiment isdifferent from the conventional LDMOSs in a point that the n-type region6 and the p⁺-type contact region 9 are formed. These regions may beformed by ion-implanting the impurity to the surface of the n-typesubstrate 1 or by diffusing in solid phase. Although the n-type region 6and the p⁺-type contact region 9 may be formed at any timing, it ispreferable to form the n-type region 6 before the n-type drain region 5,the n-type source region 8 and the p⁺-type contact region 9 because ittakes long time needs to be thermally diffused.

[0098]FIGS. 5 through 8 show one exemplary manufacturing steps of theLDMOS illustrated in the present embodiment and the manufacturing methodof the LDMOS will be explained. It is noted that trenches and othersrelated to the trenches which insulate the LDMOS from the other elementregions will be illustrated here.

[0099] [Step in FIG. 5a]

[0100] The SOI substrate having the insulating film 3 such as an oxidefilm and an n⁻-type epi-layer (or the n-type substrate) 1 on the p-typesubstrate 2 is prepared at first. The n⁻-type epi-layer 1 has a n-typeimpurity concentration of 1×10¹⁵ cm⁻³ and a thickness of approximately10 μm. The -oxide film 3 has a thickness of about 2 μm.

[0101] [Step in FIG. 5b]

[0102] A trench 20 which reaches the insulating film 3 is formed byphoto-etching the n−-type epi-layer 1. Then, the surface of the n-typesubstrate 1 including the inner wall of the trench 20 is thermallyoxidized to cover the inner wall by a thermal oxide film 21. An elementseparating region is formed by depositing a polysilicon film 22 so as tobury the inside of the trench 20.

[0103] [Step in FIG. 5c]

[0104] The p-type impurity, e.g., boron, is ion-implanted selectively atan outer periphery region of the LDMOS, and then a n-type impurity,e.g., phosphorus, is ion-implanted selectively on the surface layer partof the n-type epi-layer 1 approximately between 2×10¹³ and 1×10¹⁴ cm⁻²of dosage. Thereby, a p-type impurity implanted layer 23 and an n-typeimpurity implanted layer 24 are formed.

[0105] Since the dosage of the n-type impurity is 1×10¹⁴ cm⁻² or less,it is possible to let sustain characteristics become positive steadilyand to prevent a depletion layer extending through the n-type region 6shown in FIG. 1 from reaching to the n⁺-type drain region 5 because theimpurity is 2×10¹³ cm⁻² or more.

[0106] It is noted that the ion-implantation of p-type impurity in thestep shown in FIG. 5c can be applied for forming a P well region in aCMOS of a complex IC when the complex IC is formed in the SOI substratetogether with the LDMOS.

[0107] [Step in FIG. 6a]

[0108] A heat treatment is carried out to thermally diffuse the bothp-type impurity and n-type impurity implanted in the step shown in FIG.5c. Thereby, the impurity in the respective impurity implanted layers 23and 24 is diffused., thus forming a p-well region 25 and an n-typeregion 26. At this time, the interface of the LOCOS oxide film becomesunstable due to a suction of the impurity to the LDMOS oxide film 4formed in the step later than the ion-implanting step shown in FIG. 6a(see FIG. 6b) when a diffusion depth of the n-type impurity is shallow,while a wide source-drain interval, which increase an ON resistance, maybe provided because an expansion of the diffusion in a lateral directionis estimated when the depth is deep. Therefore, it is preferable to setthe diffusion depth approximately between 2 and 4 μm. It is noted thatthe width of the n-type region 6 is controlled corresponding to therequired capacity for pressure because the capacity for pressure iscontrolled by the width of the n-type region 6.

[0109] [Step in FIG. 6b]

[0110] After forming the oxide film and the nitride film in turn,predetermined regions of the nitride film between the n⁺-type drainregion 5 and the p-type base region 7 and the p-type well region 25formed in the later steps (see FIGS. 7c and 8 a) are removed. Then, athermal oxidization is carried out. After that, the oxide and nitridefilms are removed. On this account, the LOCOS oxide film 4 is formedbetween the n⁺-type drain region 5 and the p-type base region 7 by theknown LOCOS method. The heat in forming the LOCOS oxide film may beutilized in a diffusion of the n-type impurity by forming the LOCOSoxide film after forming the n-type region 6.

[0111] [Step in FIG. 6c]

[0112] The gate insulating film 10 is formed between the LDMOS oxidefilms 4 by thermal oxidation and the like.

[0113] [Step in FIG. 7a]

[0114] A gate electrode 11 is formed by patterning a polysilicon filmafter depositing the polysilicon film on the gate insulating film 10 andthe LOCOS oxide film 4.

[0115] [Step in FIG. 7b]

[0116] Boron is ion-implanted as a p-type impurity by using the gateelectrode as a mask. Then, the p-type base region 7 is formed bythermally diffusing the implanted boron. At this time, it is preferableto set a diffusion depth at approximately 2 μm, a diffusion temperatureat 1000° C. or more and a diffusion time at 2 hours or more.

[0117] [Step in FIG. 7c]

[0118] Boron, for example, is ion-implanted into a source forming regionas a p-type impurity by using the gate electrode as a mask. Then, thep⁺-type contact region 9 is formed by thermally diffusing the implantedboron. A dosage of boron at this time is more than 2×10¹⁵ cm⁻² and lessthan 5×10¹⁵ cm⁻². A depth of diffusion is more than 0.3 μm and less than1 μm. A surface concentration of the p⁺-type contact region 9 isapproximately 1×10¹⁸ cm⁻³ or, is preferably 1×10¹⁸ cm⁻³ or more more. Itis also arranged that the implanted p-type impurity does not reach belowthe gate electrode 11 after the thermal diffusion by setting itsdiffusion temperature to be lower than the diffusion temperature informing the p-type base region 7 or setting its diffusion time to beshorter than the diffusion time in forming the p-type base region 7 andby selecting a width of the mask of the ion-implanted part. It is notedthat the p⁺-type contact region 9 is prevented from diffusingexcessively by the heat in forming the p-type base region 7 because thisstep for forming the p⁺-type contact region 9 is carried out afterforming the p-type base region 7.

[0119] [Step in FIG. 8a]

[0120] A high concentrate p⁺-type region 9 a is formed in a surfacelayer part of the p⁺-type contact region 9 by ion-implanting boron asthe p-type impurity. The n⁺-type source region 8 and the n⁺-type drainregion 5 are formed by ion-implanting arsenic as a n-type impurity to apart of the p⁺-type contact region 9 surrounding the p⁺-type region 9 aand to the n-type region 6. At this time, the n⁺-type drain region 5 isdiffused under the insulating film 4 with a self-alignment by using theinsulating film 4 as a mask.

[0121] [Step in FIG. 8b]

[0122] Contact holes each connected with the n⁺-type drain region 5, thep⁺-type contact region 9 and the n⁺-type source region 8 is formed byselectively removing the interlayer insulating film 12 after forming theinterlayer insulating film 12 composed of a BPSG film and others on thewhole upper surface of the substrate including the gate electrode 11.

[0123] [Step in FIG. 8c]

[0124] The source electrode 13 electrically connected with the p⁺-typecontact region 9 and the n⁺-type source region 8 via the contact hole isformed and the drain electrode 14 electrically connected with then⁺-type drain region 5 is formed by patterning an Al film afterdepositing an Al film on the interlayer insulating film 12.

[0125] Thus, the LDMOS whose capacity for ESD surge is improved as shownin FIG. 1 is fabricated. It is noted that although the deep base layershown in FIG. 1 is omitted in FIGS. 5 through 8, the deep base layer maybe formed in the step shown in FIG. 5c by dividing a width and a rangeof ion-implantation into two steps.

[0126] It is noted that although the concentration profile of the n-typeregion 6 is approximately 5×10¹⁶ to 2×10¹⁷ cm⁻³ in the embodimentdescribed above, it is merely an illustration and the current valuecoming into the negative resistance region may be rised as long as then-type region 6 is constructed such that at least its concentration ishigher than that of the n-type substrate 1 and gradually increases fromthe n-type substrate 1 to the n⁺-type drain region 5.

[0127] Further, although the p⁺-type contact region 9 extends below then⁺-type source region 8 in the embodiment described above, the sameeffect with the above embodiment may be obtained by forming a p⁺-typeregion beside the p⁺-type contact region 9 and by disposing it so as tocontact with the under part of the n⁺-type source region 8.

[0128] Although the SOI substrate in which the oxide film and the n-typeepi-layer are formed on the p-type substrate is applied to oneembodiment for this invention, a buried n⁺-type layer 30 may be formedat an interface portion the n-type substrate 1 with the oxide film asshown in FIG. 9. An n-type drift layer 31 whose concentration is higherthan that of the n-type epi-layer 1 may be also formed on an upperportion of the n-type epi-layer 1 as shown in FIG. 10.

[0129] It is also possible to carry out high-accelerationion-implantation when the p⁺-type contact region 9 is formed as shown inFIG. 7c and to bring a center range at a part about 1 μm from thesurface of the n-type epitaxial layer 1 as shown in FIG. 11. In thisway, the concentration of the channel part can be suppressed low even ifthe concentration of the p⁺-type contact region 9 is increased. It isnoted that it is preferable to carry out the ion-implantation from avertical direction in forming the p⁺-type contact region 9.

[0130] Further, the LDMOS illustrated in the embodiments described abovemay be formed together with a P-channel MOS transistor as shown in FIG.12 in which a p⁺-type source region 41 and a p⁺-type drain region 42 areformed on a surface layer part of an n-type layer 31 which is formed inan upper portion of the n-type epi-layer 1, a gate electrode 44 isformed on a channel region between the p⁺-type source region 41 and thep⁺-type drain region 42 through a gate oxide film 43 and a sourceelectrode 46 and a drain electrode 47 are formed through an interlayerinsulating film 45. In this case, it is possible to share the step forforming the n-type region 6 provided in the LDMOS and the step forforming n-type region 48 disposed between neighboring cells, i.e.,between a source of one P-channel MOS transistor and a drain of theother P-channel MOS transistor adjacent to the one P-channel MOStransistor in concrete. It allows the manufacturing steps to besimplified.

[0131] It is noted that although the n-channel type LDMOS has beenexplained above, the present invention is also applicable to a p-channeltype LDMOS in which the conductive type is inverted.

What is claimed is:
 1. A semiconductor device, comprising: a substratehaving a first conductive type semiconductor layer; a second conductivetype base region formed on said semiconductor layer; a first conductivesource region formed on said base region; a first conductive type drainregion disposed so as to separate from said base region on saidsemiconductor layer; a gate insulating film formed on a channel regionof said base region positioned between said source region and said drainregion; a gate electrode formed on said gate insulating film; a sourceelectrode connected with said source region; a drain electrode connectedwith said drain region; a first conductive type region provided on saidsemiconductor layer so as to be disposed between said drain region andsaid base region; and wherein said first conductive type region has animpurity concentration higher than that of said semiconductor layer,wherein the impurity concentration gradually increases from thesemiconductor layer to said drain region.
 2. A semiconductor device,comprising: a substrate having a first conductive type semiconductorlayer; a second conductive type base region formed on said semiconductorlayer; a first conductive type source region formed on said base region;a first conductive type drain region disposed so as to separate fromsaid base region on said semiconductor layer; a gate insulating filmformed on a channel region of said base region positioned between saidsource region and said drain region; a gate electrode formed on saidgate insulating film; a source electrode connected with said sourceregion; a drain electrode connected with said drain region; and a firstconductive type region provided on said semiconductor layer so as tosurround said drain region; wherein said first conductive type regionhas an impurity concentration than that of said semiconductor layer,wherein the concentration gradually increases from the semiconductorlayer to said drain region.
 3. The semiconductor device according toclaim 1, wherein a predetermined concentration of a part of said firstconductive type region near said drain region is approximately between5×10¹⁶ and 2×10¹⁷ cm⁻³.
 4. The semiconductor device according to claim2, wherein a predetermined concentration of a part of said firstconductive type region near said drain region is approximately between5×10¹⁶ and 2×10¹⁷ cm⁻³.
 5. The semiconductor device according to any oneof claims 1, wherein a region whose concentration is lower than that ofsaid first conductive type region is provided between said firstconductive type region and said base region.
 6. The semiconductor deviceaccording to claim 5, wherein the impurity concentration in the regionwhose concentration is lower than that of said first conductive typeregion is approximately between 1×10¹⁵ and 1×10¹⁶ cm⁻³.
 7. Thesemiconductor device according to claim 1, further comprising: a secondconductive type region contacting with the lower part of said sourceregion, and having a concentration higher than that of said base region.8. The semiconductor device according to claim 2, further comprising: asecond conductive type region contacting with the lower part of saidsource region, and having a concentration higher than that of said baseregion.
 9. The semiconductor device according to claim 7, wherein saidsecond conductive type region is disposed away from said channel region.10. The semiconductor device according to claim 8, wherein said secondconductive type region is disposed away from said channel region. 11.The semiconductor device according to claim 1, further comprising: asecond conductive type contact region disposed adjacent to said sourceregion, said second conductive type contact region provided on a surfacelayer of said base region; wherein said second conductive type contactregion and said source region connects to said source electrode; whereinsaid second conductive type contact region has a concentration higherthan that of said base region and extends under said source region. 12.The semiconductor device according to claim 2, further comprising: asecond conductive type contact region disposed adjacent to said sourceregion, said second conductive type contact region provided on a surfacelayer of said base region; wherein said second conductive type contactregion and said source region connects to said source electrode; whereinsaid second conductive type contact region has a concentration higherthan that of said base region and extends under said source region. 13.The semiconductor device according to claim 11, wherein said contactregion is connected with said source electrode on an opposite side ofsaid semiconductor layer from said drain region, whereby said sourceregion is positioned between said contact region and the drain region.14. The semiconductor device according to claim 12, wherein said contactregion is connected with said source electrode on an opposite side ofsaid semiconductor layer from said drain region, whereby said sourceregion is positioned between said contact region and the drain region.15. A semiconductor device, comprising: a substrate having a firstconductive type semiconductor layer; a second conductive type baseregion formed on said semiconductor layer; a first conductive typesource region formed on said base region; a first conductive type drainregion disposed so as to separate from said base region on saidsemiconductor layer; a gate insulating film formed on a channel regionof said base region positioned between said source region and said drainregion; a gate electrode formed on said gate insulating film; a sourceelectrode connected with said source region; a drain electrode connectedwith said drain region; and a second conductive type region having aconcentration higher than that of said base region, and contacting witha lower part of the source region.
 16. A semiconductor device,comprising: a substrate having a first conductive type semiconductorlayer; a second conductive type base region formed on said semiconductorlayer; a first conductive type source region formed on said base region;a first conductive type drain region disposed so as to separate fromsaid base region on said semiconductor layer; a gate insulating filmformed on a channel region of said base region positioned between saidsource region and said drain region; a gate electrode formed on saidgate insulating film; a source electrode connected with said sourceregion; and a drain electrode connected with said drain region; a secondconductive type contact region having a concentration higher than thatof said base region and disposed adjacent to said source region, saidsecond conductive type contact region connected with said sourceelectrode together with said source region; wherein said secondconductive type region contacts with a lower part of the source region.17. A method for manufacturing a semiconductor device, comprising:forming a first conductive type region on a surface layer part of asemiconductor layer; forming a oxide film on a part of said firstconductive type region and a part of said semiconductor layer containingsaid first conductive type region; forming a gate insulating film onsaid semiconductor layer; forming a gate electrode on said gateinsulating film; forming a second conductive type base region on asurface layer part of said semiconductor layer by using said gateelectrode as a mask; forming a second conductive type contact regionwhose concentration is higher than that of said base region within saidbase region; forming a first conductive type source region within saidbase region and forming a first conductive type drain region whoseconcentration is higher than that of said first conductive type regionwithin said first conductive type region; forming an interlayerinsulating film on said substrate that covers the gate electrode;forming a source electrode electrically connected with said sourceregion and said contact region; and forming a drain electrodeelectrically connected with said drain region.
 18. The method formanufacturing the semiconductor device according to claim 17, whereinthe step for forming said first conductive type region is carried out byion-implanting to a first conductive type impurity level, wherein adosage of said first conductive type impurity level is set at 1×10¹⁴cm⁻² or less.
 19. The method for manufacturing the semiconductor deviceaccording to claim 18, wherein the dosage of said first conductive typeimpurity is set at 2×10¹³ cm⁻² or more.
 20. The method for manufacturingthe semiconductor device according to claim 17, wherein a depth of saidfirst conductive type region is set at 2 to 4 μm.
 21. The method formanufacturing the semiconductor device according to claim 17, whereinthe step for forming said first conductive type region is carried outbefore the step for forming said oxide film.
 22. The method formanufacturing a semiconductor device according to claim 17, wherein thestep for forming said contact region is carried out after the step forforming said base region.
 23. The method for manufacturing asemiconductor device according to claim 17, wherein the step for formingsaid contact region is carried out by ion-implanting to a secondconductive type impurity level, wherein a dosage of said secondconductive type impurity level is set at 2×10¹⁵ cm⁻² or more.
 24. Themethod for manufacturing the semiconductor device according to claim 23,wherein the step for forming said contact region is carried out by highacceleration ion implantation.
 25. The method for manufacturing thesemiconductor according to claim 17, wherein a depth of said contactregion is 1 μm or less.
 26. The method for manufacturing thesemiconductor according to claim 17, further comprising: forming a CMOSdevice by forming a first conductive type well region disposed betweenneighboring cells; wherein the step for forming the first conductivetype well region is performed by the step for forming said firstconductive type region.
 27. The method for manufacturing thesemiconductor according to claim 17, wherein said semiconductor layer isformed on a semiconductor substrate and an insulating film, wherein saidinsulating film is positioned between said semiconductor layer and saidsemiconductor substrate.